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data sheet mpc9447 revision 8 december 21, 2012 1 ?2012 integrated device technology, inc. 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer mpc9447 nrnd the freescale semiconductor, inc. mpc9447 is a 3.3 v or 2.5 v compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. with output frequencies up to 350 mhz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. features ? 9 lvcmos compatible clock outputs ? 2 selectable, lvcmos compatible inputs ? maximum clock frequency of 350 mhz ? maximum clock skew of 150 ps ? synchronous output stop in logic low state eliminates output runt pulses ? high-impedance output control ? 3.3 v or 2.5 v power supply ? drives up to 18 series terminated clock lines ? ambient temperature range -40 ? c to +85 ? c ? 32-lead lqfp packaging, pb-free ? supports clock distribution in networking, telecommunications, and computer applications ? pin and function compatible to mpc947 functional description mpc9447 is specifically designed to distribute lvcmos compatible clock signals up to a frequency of 350 mhz. each output provid es a precise copy of the input signal with a near zero skew. the outputs buffers support driving of 50 ? terminated transmission lines on the incident edge. each is capable of driving either one parallel terminated or two series terminated transmission lines. two selectable independent lvcmos compatible clock inputs are available, providing support of redundant clock source systems. t he mpc9447 clk_st op control is synchronous to the falling edge of the input clock. it allows the start and stop of the output clock signal only in a logic low state, and thus, eliminates potential output runt pulses. applying the oe control will force the outputs into hi gh-impedance mode. all inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. the device supports a 2.5 v or 3.3 v power supply and an ambient temperature range of -40 ? c to +85 ? c. the mpc9447 is pin and function compatible but performance-enhanced to the mpc947. ac suffix 32-lead lqfp package pb-free package case 873a-03 low voltage 3.3 v/2.5 v lvcmos 1:9 clock fanout buffer nrnd ? not recommend for new designs
mpc9447 revision 8 december 21, 2012 2 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer figure 1. logic diagram figure 2. 32-lead pinout (top view) 0 1 cclk0 cclk1 clk_sel clk_stop oe q0 q1 q2 q3 q4 q5 q6 q7 q8 v cc v cc 25k v cc 25k v cc clk stop sync (all input resistors have a value of 25 k ? ) gnd q2 v cc q1 gnd q0 v cc gnd q6 v cc q7 gnd q8 gnd q3 v cc q4 gnd q5 v cc gnd gnd clk_sel cclk0 cclk1 clk_stop oe v cc gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mpc9447 gnd v cc gnd table 1. function table control default 0 1 clk_sel 1 clk0 input selected clk1 input selected oe 1 outputs disabled (high-impedance state) (1) 1. oe = 0 will high-impedance tristate all outputs independent on clk_stop. outputs enabled clk_stop 1 outputs synchronously stopped in logic low state outputs active table 2. pin configurations pin i/o type function cclk0 input lvcmos clock signal input cclk1 input lvcmos alternative clock signal input clk_sel input lvcmos clock input select clk_stop input lvcmos clock output enable/disable oe input lvcmos output enable/disable (high-impedance tristate) q0?8 output lvcmos clock outputs gnd supply ground negative power supply (gnd) v cc supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation
mpc9447 revision 8 december 21, 2012 3 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf inputs table 4. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these c onditions or conditions beyond those indicated may adversely affect device reliability. functional operation at absolute-maximum-rated condi tions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current ? 20 ma i out dc output current ? 50 ma t s storage temperature ?65 125 ? c table 5. dc characteristics (v cc = 3.3 v 5%, t a = -40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.8 v lvcmos v oh output high voltage 2.4 v i oh = ?24 ma (1) 1. the mpc9447 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines (for v cc = 3.3 v). v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 17 ? i in input current (2) 2. inputs have pull-down or pull-up resistors affecting the input current. ? 300 ? a v in = v cc or gnd i ccq maximum quiescent supply current (3) 3. i ccq is the dc current consumption of the device with all outputs open and the input in its default state or open. 2.0 ma all v cc pins
mpc9447 revision 8 december 21, 2012 4 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer table 6. ac characteristics (v cc = 3.3 v 5%, t a = -40c to +85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f ref input frequency 0 350 mhz f max output frequency 0 350 mhz f p,ref reference input pulse width 1.4 ns t r , t f cclk0, cclk1 input rise/fall time 1.0 (2) 2. violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device ske w, reference input pulse width, output duty cycle and maximum frequency specifications. ns 0.8 to 2.0 v t plh/hl propagation delay cclk0 or cclk1 to any q 1.3 3.3 ns t plz, hz output disable time 11 ns t pzl, zh output enable time 11 ns t s setup time cclk0 or cclk1 to clk_stop (3) 3. setup and hold times are referenced to the falling edge of the selected clock signal input. 0.0 ns t h hold time cclk0 or cclk1 to clk_stop (3) 1.0 ns t sk(o) output-to-output skew 150 ps t sk(pp) device-to-device skew 2.0 ns t sk(p) dc q output pulse skew (4) output duty cycle f q <170 mhz 4. output pulse skew is the absolute difference of the propagation delay times: | t plh ? t phl |. 45 50 300 55 ps % dc ref = 50% t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4 v t jit buffer additive phase jitter, rms 0.03 ps 156.25mhz, integration range: 12khz - 20mhz table 7. dc characteristics (v cc = 2.5 v 5%, t a = -40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.7 v lvcmos v oh output high voltage 1.8 v i oh = ?15 ma (1) 1. the mpc9447 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives one 50 ? series terminated transmission lines per output (v cc = 2.5 v). v ol output low voltage 0.6 v i ol = 15 ma z out output impedance 19 ? i in input current (2) 2. inputs have pull-down or pull-up resistors affecting the input current. ? 300 ? a v in = v cc or gnd i ccq maximum quiescent supply current (3) 3. i ccq is the dc current consumption of the device with all outputs open and the input in its default state or open. 2.0 ma all v cc pins
mpc9447 revision 8 december 21, 2012 5 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer table 8. ac characteristics (v cc = 2.5 v 5%, t a = -40c to +85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f ref input frequency 0 350 mhz f max output frequency 0 350 mhz f p,ref reference input pulse width 1.4 ns t r , t f cclk0, cclk1 input rise/fall time 1.0 (2) 2. violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device ske w, reference input pulse width, output duty cycle and maximum frequency specifications. ns 0.7 to 1.7 v t plh/hl propagation delay cclk0 or cclk1 to any q 1.7 4.4 ns t plz, hz output disable time 11 ns t pzl, zh output enable time 11 ns t s setup time cclk0 or cclk1 to clk_stop (3) 3. setup and hold times are referenced to the falling edge of the selected clock signal input. 0.0 ns t h hold time cclk0 or cclk1 to clk_stop (3) 1.0 ns t sk(o) output-to-output skew 150 ps t sk(pp) device-to-device skew 2.7 ns t sk(p) dc q ouput pulse skew (4) output duty cycle f q <350 mhz 4. output pulse skew is the absolute difference of the propagation delay times: | t plh ? t phl |. 45 50 200 55 ps % dc ref = 50% t r , t f output rise/fall time 0.1 1.0 ns 0.6 to 1.8 v t jit buffer additive phase jitter, rms 0.03 ps 156.25mhz, integration range: 12khz - 20mhz
mpc9447 revision 8 december 21, 2012 6 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer application information figure 3. output clock stop ( clk_stop) timing diagram driving transmission lines the mpc9447 clock driver was designed to drive high-speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of 17 ? (v cc = 3.3 v), the outputs can drive either parallel or series terminated transmission lines. for more information on transmission lines, the reader is referred to freescale application note an1091. in most high performance clock networks, point-to-point distribution of signals is the method of choice. in a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc ? 2. figure 4. single versus dual transmission lines this technique draws a fairly high level of dc current, and thus, only a single terminated line can be driven by each output of the mpc9447 clock driver. for the series terminated case, however, there is no dc current draw; thus, the outputs can drive multiple series terminated lines. figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, the fanout of the mpc9447 clock driver is effectively doubled due to its capability to drive multiple lines at v cc = 3.3 v. figure 5. single versus dual line termination waveforms the waveform plots in figure 5 show the simulation results of an output driving a single line versus two lines. in both cases, the drive capability of the mpc9447 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulation,s a delta of only 43 ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the mpc9447. the output waveform in figure 5 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 33 ? series resistor, plus the output impedance, does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l = v s (z 0 ? (r s +r 0 +z 0 )) z 0 = 5 0 ? || 50 ? r s = 33 ? || 33 ? r 0 = 1 7 ? v l = 3.0 (25 ? (16.5+17+25) = 1.28 v at the load end, the voltage will double, due to the near unity reflection coefficient, to 2.5 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). cclk0 or cclk1 clk_stop q0 to q8 17 ? in mpc9447 output buffer r s = 33 ? z o = 50 ? outa 17 ? in mpc9447 output buffer r s = 33 ? z o = 50 ? outb0 r s = 33 ? z o = 50 ? outb1 time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in
mpc9447 revision 8 december 21, 2012 7 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines, the situation in figure 6 should be used. in this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. figure 6. optimized dual line termination the following figures illustrate the measurement reference for the mpc9447 clock driver circuit figure 7. cclk mpc9447 ac test reference for v cc = 3.3 v and v cc = 2.5 v 17 ? mpc9447 output buffer r s = 16 ? z o = 50 ? r s = 16 ? z o = 50 ? 17 ?? + 16 ? || 16 ? = 50 ? || 50 ? 25 ? = 25 ? pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? mpc9447 dut v tt v tt
mpc9447 revision 8 december 21, 2012 8 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer figure 8. propagation delay (t pd ) test reference figure 9. output-to-output skew t sk(lh, hl) figure 10. output pulse skew (t sk(p) ) test reference figure 11. output duty cycle (dc) figure 12. output transition time test reference figure 13. cycle-to-cycle jitter figure 14. setup and hold time (t s , t h ) test reference v cc v cc ? 2 gnd v cc v cc ? 2 gnd cclk q x t p(lh) t p(hl) the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. v cc v cc ? 2 gnd v cc v cc ? 2 gnd t sk(lh) t sk(hl) v cc v cc ? 2 gnd v cc v cc ? 2 gnd t p(lh) cclk q x t p(hl) t sk(p) = | t plh ? t phl | the time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage. v cc v cc ? 2 gnd t p t 0 dc = (t p ? t 0 x 100%) t f t r v cc =3.3 v v cc =2.5 v 2.4 1.8 v 0.55 0.6 v the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. t n t jit(cc) = | t n -t n+1 | t n+1 v cc v cc ? 2 gnd v cc v cc ? 2 gnd t s cclk pclk clk_stop t h
package dimensions mpc9447 revision 8 december 21, 2012 9 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer 12 ref dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.08 --- 0? 7? 9.00 bsc 7.00 bsc 0.50 0.70 q q 0.20 ref d1 d/2 e e1 1 8 9 17 25 32 d1/2 e1/2 e/2 4x d 7 a d b a-b 0.20 h d 4x a-b 0.20 c d 6 6 4 4 detail g pin 1 index detail ad r r2 ? (s) l (l1) 0.25 gauge plane a2 a a1 ( 1?) 8x r r1 e seating plane detail ad 0.1 c c 32x 28x h detail g f f e/2 a, b, d 3 section f-f base c1 c b b1 metal a-b m 0.20 d c 5 8 plating notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08-mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07-mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25-mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1-mm and 0.25-mm from the lead tip. case 873a-03 issue b 32-lead lqfp package
mpc9447 revision 8 december 21, 2012 10 ?2012 integrated device technology, inc. mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer revision history sheet rev table page description of change date 7 t6, t8 1 2 4, 5 6 functional description - corrected pin name clk_stop to clk_stop. logic diagram (fig 1) - corrected pin name clk_stop to clk_stop and deleted bar from pin 1, 2, 3, 4, 6, 9, 11, 20, 25. ac characteristics table - corrected pin name clk_stop to clk_stop. figure 3 diagram and title - corrected pin name clk_stop to clk_stop. 9/12/11 8 1 removed leaded part information 11/16/12 8 1 nrnd ? not recommend for new designs 12/21/12
mpc9447 data sheet 3.3v, 2.5v, 1:9 lvcmos clock fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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